Power-aware branch target prediction using a new BTB architecture

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using SimpleScalar and Wattch performance and power tools. The simulation experiment results show that the first method decreases power about 3% and the second method decreases power consumption of BTB up to 7.3%. Moreover, combining these two methods would reduce power consumption of BTB up to 8.3% without affecting performance of the processor.

1. Introduction

The accuracy of branch prediction plays a key role in the performance of current processors which their pipeline length is growing [5], [8], [14], [17]. Moreover, the power consumption of the branch predictors should be reduced since they contribute more than 10% of total power consumed in the processors [2], [15], [16].