Implementing Root Raised Cosine (RRC) filter for WCDMA using Xilinx

This paper presents implementation of Root Raised Cosine (RRC) filter at transmitter of 3G-WCDMA wireless communication by using VHDL programming language on Field Programmable Logic Array (FPGA). The main objective of this project is to reduce the inter-symbol interference (ISI) which will affect the bandwidth required for transmission the data. MATLAB 7.0 is used to design RRC filter for generating filter coefficient and checking its functionality in WDCMA transmitter. Then RRC filter coding is generated by VHDL in XILINX application and being verified in Model Sim SE 6.3f before it being synthesized using Xilinx ISE Simulator. All the results produced will be verified for make a comparison.

I. Introduction

THE need to enhance an efficient communication is one of t^he prime necessities of people today. Third generation (3G) wireless communications using WCDMA will offer wide band data and voice services that will enable applications such as wireless video conferencing and Internet. The WCDMA standard has two modes for the duplex method Frequency Division Duplex (FDD) and Time Division Duplex (TDD). The frequency bands allocated for WCDMA are shown in Figure 1 [2]. In WCDMA there is one pair frequency band in the range 1920–1980 MHz and 2110 – 2170 MHz to be used for WCDMA FDD. There are two unpaired bands from 1900 – 1920 MHz and 2010–2025 MHz intended for the operation of WCDMA TDD. Figure 1:

The frequency spectrum allocations for WCDMA table 1: Standardize parameter for WCDMA