Abstract:
Unlike static CMOS circuits, the standby energy in sense amplifier-based pass transistor logic (SAPTL) circuits can be decoupled from its performance, allowing separate o...Show MoreMetadata
Abstract:
Unlike static CMOS circuits, the standby energy in sense amplifier-based pass transistor logic (SAPTL) circuits can be decoupled from its performance, allowing separate optimization strategies for leakage and speed. In this paper, a 64-byte parallel cyclic-redundancy check (CRC) generator is designed and implemented using asynchronous 90nm SAPTL circuits, with a simulated minimum energy point that is 25% lower than the equivalent complementary static CMOS implementation. The low leakage operation results in (a) an 7.9X reduction in measured energy when VDD is reduced from 1V to 0.3V at α = 0.1 and (b) a 10% reduction in measured delay with a stack forward body bias of 0.4V, with no corresponding increase in energy.
Date of Conference: 15-18 May 2011
Date Added to IEEE Xplore: 04 July 2011
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Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
Contents Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
Berkeley Wireless Research Center, University of California Berkeley, Berkeley, CA, USA
