CMOS DAC-sharing stimulator for neural recording and stimulation arrays | IEEE Conference Publication | IEEE Xplore

CMOS DAC-sharing stimulator for neural recording and stimulation arrays


Abstract:

A compact biphasic neural stimulator for use in multi-channel integrated neural recording and stimulation interfaces is presented. The stimulator is a part of an envision...Show More

Abstract:

A compact biphasic neural stimulator for use in multi-channel integrated neural recording and stimulation interfaces is presented. The stimulator is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The stimulator reuses the capacitive DAC inside the recording SAR ADC to provide 8-bit current amplitude resolution and reconfigures the digital SAR controller logic to provide 4-bit tunability of the duty cycle of the current pulse. A voltage-to-current converter and a current driver are the only additional circuits required. An OTA is reused to provide accurate current matching and to remove excess charge on the electrode. The stimulator is implemented in a standard 0.13μm CMOS technology. Post-layout and Monte Carlo simulation results show 8-bit functionality from 5μA to 1.2mA, a 2.5V swing and 1 percent current matching between positive and negative pulses.
Date of Conference: 15-18 May 2011
Date Added to IEEE Xplore: 04 July 2011
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Conference Location: Rio de Janeiro, Brazil
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada

Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
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