Abstract:
To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete c...Show MoreMetadata
Abstract:
To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete chip area is divided into distinguishable subchips, each containing one large area power MOS-transistor. The fast digital measurements and the precise localization of transistor short circuits guarantee a fast process classification and enable additional electrical and optical defect parameter extraction.
Date of Conference: 17-20 March 1997
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3243-1