Performance, process architecture, and tooling considerations for advanced semiconductor wafer fabs

Results of a study of designing high-performance advanced semiconductor wafer fabs are presented focusing on the underlying process architecture and tooling considerations. Processing framework of 0.35 micron technology suitable for ASIC, microprocessor and SRAM manufacturing is discussed. Results of the modeling and simulation of equipment and fab operation are presented which were used to determine the minimum feasible equipment complement required for the target volume requirements of 500 wafer starts per day. These results confirm that the proposed wafer fab for the 0.35 micron process technology is capable of achieving low-cycle times under 2/spl times/ of the raw process time or about 1 week of the calendar time. This rapid cycle time is primarily due to the maximum use of the integrated cluster tools.