Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation

Hold timing closure and scan power are major concerns for any design. Hold closure for scan shift operation generally causes addition of buffers in the data path between flip-flops. This results in increased gate count that will toggle during the functional mode of operation thereby resulting in an increase in functional power. Scan operation also causes higher switching activity due to high toggling in a given test cycle. There are two components of power i.e. peak power and average power. Peak power increases IR-drop in the design, thereby reducing the voltage across the transistor and can lead to failure. In this paper we will present a modified flip-flop architecture that will serve two purposes i.e. enabling hold timing closure across process, voltage, temperature and reducing peak power during scan shift operation with minimal impact to functional timing and area. The modified flip-flop will introduce a half cycle delay in the data path invariant of process, voltage, temperature thereby easing hold closure. Test time and coverage are not impacted by the same. Existing ATPG tool generated pattern can be applied with this scheme. This approach reduces peak power close to 50% and reduces hold buffer area close to 40% in a given design.