Abstract:
Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that ...Show MoreMetadata
Abstract:
Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.
Published in: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Date of Conference: 13-15 April 2011
Date Added to IEEE Xplore: 31 May 2011
ISBN Information:
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Path Length ,
- Version Of Test ,
- Inaccurate Model ,
- Manufacturing Defects ,
- Running Time ,
- Greater Than Or Equal ,
- Input Vector ,
- Length Range ,
- Overview Of Methods ,
- Time In Seconds ,
- Test Pattern ,
- Output Gate ,
- Boolean Variable ,
- Primary Input ,
- Binary Search ,
- Primary Output ,
- Target Length ,
- Circuit Size ,
- Path Segment ,
- Real Depth ,
- Valid Path ,
- Sum Of Delay
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Path Length ,
- Version Of Test ,
- Inaccurate Model ,
- Manufacturing Defects ,
- Running Time ,
- Greater Than Or Equal ,
- Input Vector ,
- Length Range ,
- Overview Of Methods ,
- Time In Seconds ,
- Test Pattern ,
- Output Gate ,
- Boolean Variable ,
- Primary Input ,
- Binary Search ,
- Primary Output ,
- Target Length ,
- Circuit Size ,
- Path Segment ,
- Real Depth ,
- Valid Path ,
- Sum Of Delay