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The programmable logic implementation of GPS/GLONASS clock synchronization | IEEE Conference Publication | IEEE Xplore

The programmable logic implementation of GPS/GLONASS clock synchronization


Abstract:

A GPS/GLONASS clock synchronization implementation based on programmable logic is presented. The GPS/GLONASS PPS (standard 1 second signal) is regarded as a reference of ...Show More

Abstract:

A GPS/GLONASS clock synchronization implementation based on programmable logic is presented. The GPS/GLONASS PPS (standard 1 second signal) is regarded as a reference of the whole clock synchronization system that consists of two levels PLL. Both the GPS/GLONASS PPS and OCXO assure the long-term stability and short-term stability of clock signals. All the digital circuit, including digital phase error discriminator, 2S-generating module, phase error detecting and controlling module, can be built in a programmable logic chip.
Date of Conference: 21-24 October 2003
Date Added to IEEE Xplore: 14 May 2020
ISBN Information:
Print ISSN: 1523-553X
Conference Location: Beijing, China

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