Abstract:
This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated hig...Show MoreMetadata
Abstract:
This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single register transfer level hardware architecture optimized in area is generated. In order to reduce the register, the steering logic, and the controller complexities, this paper proposes a joint-scheduling algorithm, which maximizes the similarities between the control steps and specific binding approaches for both operators and storage elements which maximize the similarities between the datapaths. It is shown through a set of test cases that the proposed approach offers significant area saving and low-performance penalties compared to both state-of-the-art techniques and dedicated mono-mode architectures.
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 29, Issue: 11, November 2010)
Embedded Computing Laboratory, CEA Saclay, Gif-sur-Yvette, France
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Caaliph Andriamisaina received the M.S degree in electronics and telecommunications from the Université de Bretagne Occidentale, Brest, France, in 2004, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2008.
In 2009, he was a Research Engineer with the Lab-STICC Laboratory, Lorient. Since 2010, he has been a Research Engineer with the Embedded Computing La...Show More
Caaliph Andriamisaina received the M.S degree in electronics and telecommunications from the Université de Bretagne Occidentale, Brest, France, in 2004, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2008.
In 2009, he was a Research Engineer with the Lab-STICC Laboratory, Lorient. Since 2010, he has been a Research Engineer with the Embedded Computing La...View more
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Philippe Coussy (M'04) received the M.S. degree in computer science from the University Paris 6, Paris, France, in 1999, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2003.
He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient, where he has lead the HLS Research Group since 2006. His current research i...Show More
Philippe Coussy (M'04) received the M.S. degree in computer science from the University Paris 6, Paris, France, in 1999, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2003.
He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient, where he has lead the HLS Research Group since 2006. His current research i...View more
French National Institute of Research in Computer Science and Control (INRIA/IRISA), University of Rennes I, Lannion, France
Emmanuel Casseau received the M.S., Ph.D., and Hab. degrees in 1990, 1994, and 2002, respectively.
He is currently a Professor with the French National Institute for Research in Computer Science and Control, University of Rennes 1, Lannion, France. From 1994 to 1996, he was a Research Engineer with ENST Bretagne, Brest, France, a graduate engineering school. From 1996 to 2006, he was an Associate Professor with the Electro...Show More
Emmanuel Casseau received the M.S., Ph.D., and Hab. degrees in 1990, 1994, and 2002, respectively.
He is currently a Professor with the French National Institute for Research in Computer Science and Control, University of Rennes 1, Lannion, France. From 1994 to 1996, he was a Research Engineer with ENST Bretagne, Brest, France, a graduate engineering school. From 1996 to 2006, he was an Associate Professor with the Electro...View more
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Cyrille Chavet (M'06) received the M.S. and M.Ph. degrees in computer science from the Université Joseph Fourrier, Grenoble, France, in 2003, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2007.
From 2003 to 2007, he was with STMicroelectronics, Crolles, France. Then, he held a post-doctoral position with the TIMA Laboratory, Grenoble, France, for a year...Show More
Cyrille Chavet (M'06) received the M.S. and M.Ph. degrees in computer science from the Université Joseph Fourrier, Grenoble, France, in 2003, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2007.
From 2003 to 2007, he was with STMicroelectronics, Crolles, France. Then, he held a post-doctoral position with the TIMA Laboratory, Grenoble, France, for a year...View more
Contents Embedded Computing Laboratory, CEA Saclay, Gif-sur-Yvette, France
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Caaliph Andriamisaina received the M.S degree in electronics and telecommunications from the Université de Bretagne Occidentale, Brest, France, in 2004, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2008.
In 2009, he was a Research Engineer with the Lab-STICC Laboratory, Lorient. Since 2010, he has been a Research Engineer with the Embedded Computing Laboratory, CEA Saclay, Paris, France. His current research interests include design tools and methodologies for digital circuits and multicores architectures design.
Caaliph Andriamisaina received the M.S degree in electronics and telecommunications from the Université de Bretagne Occidentale, Brest, France, in 2004, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2008.
In 2009, he was a Research Engineer with the Lab-STICC Laboratory, Lorient. Since 2010, he has been a Research Engineer with the Embedded Computing Laboratory, CEA Saclay, Paris, France. His current research interests include design tools and methodologies for digital circuits and multicores architectures design.View more
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Philippe Coussy (M'04) received the M.S. degree in computer science from the University Paris 6, Paris, France, in 1999, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2003.
He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient, where he has lead the HLS Research Group since 2006. His current research interests include system-level design methodologies, high-level synthesis, and low-power design for field programmable gate arrays.
Dr. Coussy is a co-editor of High-Level Synthesis: From Algorithm to Digital Circuit (Berlin, Germany: Springer, 2008) and is a Guest Editor of the IEEE Design and Test of Computers Magazine special issue on High-Level Synthesis (July-August, 2009).
Philippe Coussy (M'04) received the M.S. degree in computer science from the University Paris 6, Paris, France, in 1999, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2003.
He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient, where he has lead the HLS Research Group since 2006. His current research interests include system-level design methodologies, high-level synthesis, and low-power design for field programmable gate arrays.
Dr. Coussy is a co-editor of High-Level Synthesis: From Algorithm to Digital Circuit (Berlin, Germany: Springer, 2008) and is a Guest Editor of the IEEE Design and Test of Computers Magazine special issue on High-Level Synthesis (July-August, 2009).View more
French National Institute of Research in Computer Science and Control (INRIA/IRISA), University of Rennes I, Lannion, France
Emmanuel Casseau received the M.S., Ph.D., and Hab. degrees in 1990, 1994, and 2002, respectively.
He is currently a Professor with the French National Institute for Research in Computer Science and Control, University of Rennes 1, Lannion, France. From 1994 to 1996, he was a Research Engineer with ENST Bretagne, Brest, France, a graduate engineering school. From 1996 to 2006, he was an Associate Professor with the Electronic Department, Université de Bretagne-Sud, Lorient, France, where he led the IP Project of the LESTER Laboratory. His current research interests include system design, high-level synthesis, systems-on-a-chip design methodologies, and reconfigurable architectures for multimedia applications.
Emmanuel Casseau received the M.S., Ph.D., and Hab. degrees in 1990, 1994, and 2002, respectively.
He is currently a Professor with the French National Institute for Research in Computer Science and Control, University of Rennes 1, Lannion, France. From 1994 to 1996, he was a Research Engineer with ENST Bretagne, Brest, France, a graduate engineering school. From 1996 to 2006, he was an Associate Professor with the Electronic Department, Université de Bretagne-Sud, Lorient, France, where he led the IP Project of the LESTER Laboratory. His current research interests include system design, high-level synthesis, systems-on-a-chip design methodologies, and reconfigurable architectures for multimedia applications.View more
Lab-STICC Laboratory, Université de Bretagne Sud, Lorient, France
Cyrille Chavet (M'06) received the M.S. and M.Ph. degrees in computer science from the Université Joseph Fourrier, Grenoble, France, in 2003, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2007.
From 2003 to 2007, he was with STMicroelectronics, Crolles, France. Then, he held a post-doctoral position with the TIMA Laboratory, Grenoble, France, for a year. He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud. His current research interests include high-level synthesis, communication adaptation, and memory mapping problems.
Cyrille Chavet (M'06) received the M.S. and M.Ph. degrees in computer science from the Université Joseph Fourrier, Grenoble, France, in 2003, and the Ph.D. degree in electrical and computer engineering from the Université de Bretagne-Sud, Lorient, France, in 2007.
From 2003 to 2007, he was with STMicroelectronics, Crolles, France. Then, he held a post-doctoral position with the TIMA Laboratory, Grenoble, France, for a year. He is currently an Associate Professor with the Lab-STICC Laboratory, Université de Bretagne-Sud. His current research interests include high-level synthesis, communication adaptation, and memory mapping problems.View more
