Optimising PROFINET IRT for fast cycle times: A proof of concept | IEEE Conference Publication | IEEE Xplore

Optimising PROFINET IRT for fast cycle times: A proof of concept


Abstract:

The PROFINET IEC 61158 standardized Real Time Ethernet (RTE) protocol, Class C, has traditionally been limited by an artificially imposed 250us cycle time, originating fr...Show More

Abstract:

The PROFINET IEC 61158 standardized Real Time Ethernet (RTE) protocol, Class C, has traditionally been limited by an artificially imposed 250us cycle time, originating from the requirement to ensure that full-sized legacy Ethernet frames can be transmitted in a single cycle through a network. Occasionally, especially in the case of high performance motion-control systems, this minimum cycle time is inadequate implying that if PROFINET is to be used in such applications either the PROFINET standard must be modified, or another protocol is used. This paper describes the implementation, in a low-cost FPGA, of a completely PROFINET compatible IP including several performance enhancements of the PROFINET standard and associated design features enabling PROFINET to be used in applications with cycle times lower than 31.25us. The paper includes a critical evaluation of the results including comparisons with other RTE protocols.
Date of Conference: 18-21 May 2010
Date Added to IEEE Xplore: 16 August 2010
ISBN Information:
Conference Location: Nancy, France

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