Replicating experimental spike and rate based neural learning in CMOS

The computational function of neural networks is thought to depend primarily on the learning/plasticity function carried out at the synapse. Neuromorphic circuit realizations have taken this into account by implementing a variety of synaptical processing functions, with most recent synapse circuits replicating some form of Spike Time Dependent Plasticity (STDP). However, STDP is being challenged by older rate-dependent learning rules as well as by biological experiments exhibiting more complex timing rules (e.g. spike triplets) as well as simultaneous rate- and timing dependent plasticity. In this paper, we present a circuit realization of a plasticity rule based on the postsynaptic neuron potential as well as the transmission profile of the presynaptic spike. To the best of our knowledge, this is the first circuit realization of synaptical behaviour which moves significantly beyond STDP, replicating the triplet experiments of Froemke and Dan, the combined timing and rate experiments of Sjoestroem et al., as well as conventional BCM behaviour.

I. Introduction

Based on experimental results, various mathematical expressions of the synaptical learning function have been proposed in literature, such as the Bienenstock-Cooper-Munroe (BCM) rule [4], STDP [5], or more involved spike timing [2] and membrane voltage [3] dependent rules. Several of those have been implemented in neuromorphic hardware to replicate their learning functions and/or computational properties [6], [7], [8], [9]. In this paper, the circuit implementation of a novel learning rule [1] based on local synaptic state variables in a UMC 130nm CMOS technology is presented. This rule can reproduce a variety of recent experimental results and is simple to implement, since it derives most of its dynamics from the neuron and the reconstruction of the incoming pulse, so the synapse complexity itself can be kept to a minimum. In Sec II, the learning rule is introduced, with circuit realizations of the waveforms necessary for its implementation given in Sec III-A. The synaptical circuit realizing the computation of the learning function is described in Sec III-B. Sec IV details results obtained when simulating the complete circuit realization using various major experimental protocols.