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Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS | IEEE Conference Publication | IEEE Xplore

Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS


Abstract:

We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual...Show More

Abstract:

We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The B-DTMOS achieved an excellent propagation delay time of 83.6 psec at 0.6 V operation and 103.3 psec at 0.5 V operation. This was realized due to ultra low body resistance of the B-DTMOS.
Date of Conference: 08-11 December 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3393-4
Print ISSN: 0163-1918
Conference Location: San Francisco, CA, USA

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