Design and Implementation of Digital Channelized Receiver in Multi-FPGA

A method of parallel processing for digital channelized receiver to complex signal is proposed to solve the problem of shortage of resources in real-time signal processing. When complex signals go through poly-phase digital channelized receiver, in order to ensure there are non-blind spots and frequency aliasing, the maximum decimation factor per channel can only be half of the number of the channels. This directly increases the data that will be processed. In order to deal with this data in specific time, the processor needs more resources or higher processing speed. The paper takes full advantage of the decimate factor and analyses the law of the convolution in the non-blind spots digital channelized receiver. The filter bank structure is achieved by using two parallel computing modules. In this way, the digital channelized receiver can be achieved in several processors simultaneously. So, the resource problem is ameliorated by this parallel implementation. Experimental results proved that the proposed method performs well in distributing the processor's resources and improving the characteristic of ultra-wideband channelized receiver, especially complex signals involved.