Gate delay time evaluation structure for deep-submicron CMOS LSIs | IEEE Conference Publication | IEEE Xplore

Gate delay time evaluation structure for deep-submicron CMOS LSIs


Abstract:

A new test structure for gate delay time measurement has been developed. The delay times of over several tens of gate chain circuits can be measured efficiently. This str...Show More

Abstract:

A new test structure for gate delay time measurement has been developed. The delay times of over several tens of gate chain circuits can be measured efficiently. This structure has common input buffers, output buffers, and a selector to avoid signal skew between each gate chain circuit. The performance of a quarter-micron SIMOX CMOS and BULK CMOS device were measured and compared with this structure.
Date of Conference: 25-28 March 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-2783-7
Conference Location: Trento, Italy

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