Gate delay time evaluation structure for deep-submicron CMOS LSIs

A new test structure for gate delay time measurement has been developed. The delay times of over several tens of gate chain circuits can be measured efficiently. This structure has common input buffers, output buffers, and a selector to avoid signal skew between each gate chain circuit. The performance of a quarter-micron SIMOX CMOS and BULK CMOS device were measured and compared with this structure.