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At-speed test on the QorIQTM P2020 platform

Colin D. Renfrew; Brian Booth; Shweta Latawa; Rick Woltenberg; Carol Pyron
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Abstract:

This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous...Show More

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Abstract:

This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.
Published in: 2009 International Test Conference
Date of Conference: 01-06 November 2009
Date Added to IEEE Xplore: 18 December 2009
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ISSN Information:

DOI: 10.1109/TEST.2009.5355588
Conference Location: Austin, TX, USA
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