High speed DDR memory interface design

Summary form only given. As the bandwidth requirement increases, Double Data Rate (DDR) interface is becoming very commonly used in many types of memories, such as, DDR I/II/III DRAM, RLDRAM I/II, QDR I/II/II+ SRAM etc. The major feature of DDR interface compared to a single data rate (SDR) one is to use both rising and falling edges of a clock to transfer data which allow it to provide two times the throughput at the same clock frequency.The high speed (up to 1.6 GHz for DDR III) nature and complex timing issues take the most attention for designers of ASIC chips with DDR memory controllers. Furthermore, the mixed signal aspect of the architecture requires careful designing or selection of I/O cells to mitigate power switching noises and manage signal integrities for the interface channel of the whole system: ASIC chip die, package, board traces and memory module / components.Multiple ways could be used in designing ASIC's with DDR memory interfaces. This tutorial will try to provide attendees some basics on the following topics: (1) Overview and Comparison of various DDR memories interfaces; (2) DDR Controller clocking scheme and strobe delay circuits; (3) Data Transmit and data capture logic implementation; (4) I/O driver impedance and receiver ODT control and calibration circuits; (5) DDR interface timing budget analysis and Chip timing constraints.