A low-frequency RFID to challenge security and privacy concerns

This paper presents a practical realization of a secure passive (battery-less) RFID tag. The tag consists of an off the shelf front end combined with a bespoke 0.18 mum ASIC assembled as a credit card sized prototype. The ASIC integrates the authors' ultra low power novel AES design together with a novel random number generator and a novel protocol which provides both security and privacy. The analysis presented shows a security of 64-bits against many attack methods. Both modeled and measured power results are presented. The measured average core power consumed during continuous normal operation is 1.36 muW.