Contents I. Introduction
Demands for high-performance, high-speed and highly-integrated semiconductor devices are significantly increased for the future information society. To meet the requests, in recent years, many researcher and product vendor have eagerly developed 3D LSIs technologies, by which all kinds of functional blocks such as processor, memory, sensor, analog and power ICs would be vertically stacked and interconnected with short TSV to give one fully-systemized IC. We have pioneered 3D integration technologies and produced 3D test chips such as vision chip and shared memories, and in addition, confirmed their basic operation [1]–[7]. The key technologies for the 3D LSI fabrication are well known to be mainly as follows: TSV formation, wafer thinning, and metal micro-bump formation. The TSV formation is the most important process technology for 3D LSI. TSV size has been significantly decreased to realize the 3D LSI having high-density TSV. The second key technology is the wafer thinning process. Approximately in chip/wafer thickness is required for the 3D integration. When chips and wafers with thicknesses of below were employed, TSV depth can be determined by approximately or more. The third key technology is metal micro-bump formation technology. Recently, Cu-Cu, Cu-Sn, Cu-Au, and In-Au micro-bumps are used for small size, low resistance and high reliability of interconnection. A number of TSVs and metal micro-bumps on the silicon substrate thinned down to can increase packing density for a vertically stacked 3D LSI, as shown in Fig.1 (a). However, this might introduce the mechanical stress and crystal defects in the thinned silicon substrate. Furthermore, active device region in the 3D LSI might be easily contaminated by metallic impurities such as Cu and Au from the back surface, as shown in Fig. 1(b). Cross-sectional structure of 3D LSI (a) and gettering effect on metal contamination from back surface after thinning (b)
