Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links

We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransporttrade (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We demonstrate production screening of 45-nm SOI-CMOS wafers at 6.4 Gb/s.

I. Introduction

Point-to-point connectivity protocols, such as HyperTrans-port™ technology [1], have become the preferred solution for delivering high-bandwidth, low-latency communication among processor dies in multi-socket systems. This approach overcomes performance limitation in legacy front-side bus architectures in which faster data transfer is impeded by the large capacitive load and half-duplex nature of long shared buses. With increasing socket counts in AMD systems, the commensurate increase in HT ports per die heightens the need for exhaustive I/O test coverage.