Abstract:
A low power and full ASIC MPEG-2/4 AAC single chip decoder is presented. The decoding blocks are partitioned into four dedicated hardware modules with the complexity and ...Show MoreMetadata
Abstract:
A low power and full ASIC MPEG-2/4 AAC single chip decoder is presented. The decoding blocks are partitioned into four dedicated hardware modules with the complexity and operational type analysis. Through algorithm, architecture, RTL and circuit level lower power techniques, the proposed AAC decoder is operated at 1.4 MHz for the 44.1 KHz sampling frequency and consumes only 0.21 mW using TSMC 0.13 mum library.
Published in: 2009 IEEE Custom Integrated Circuits Conference
Date of Conference: 13-16 September 2009
Date Added to IEEE Xplore: 09 October 2009
ISBN Information:
Contents 