A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

A class-E power amplifier is proposed in this study. It uses both nMOS and pMOS as switching devices to reduce the voltage stress of each transistor. A voltage-combining scheme with nMOS and pMOS is proposed, and a transformer is designed using this scheme. The power amplifier is implemented in a 0.18-$\mu{\hbox{m}}$ RF CMOS process. Measurements show a maximum output power of 30.2 dBm with 36.8% power-added efficiency at a 3.3-V supply voltage. The power amplifier sustains a supply voltage of up to 3.9 V.

I. Introduction

Recent progress toward single-chip radios has been made owing to the development of the CMOS process. For example, shortening the gate length leads to improvement in the MOSFET performance, as measured by the variables and . While other small-signal RF blocks benefit from the development of CMOS technology, the lowered supply voltage makes it more difficult for RF power amplifiers to generate higher output power. In fact, the power amplifier is considered one of the bottlenecks in the performance of a true single-chip radio. A power amplifier in a CMOS process has weak points compared to its counterpart in compound processes due to such factors as the lossy substrate, low quality () factor, and low breakdown voltage of active devices. Thus, designing a CMOS power amplifier remains a challenging task. Nevertheless, several studies have shown that voltage-combining methods provide a viable means of achieving watt-level output power in CMOS power amplifiers [1]– [6].