Novel technique to reduce latch-up risk due to ESD protection devices in Smart Power technologies | IEEE Conference Publication | IEEE Xplore

Novel technique to reduce latch-up risk due to ESD protection devices in Smart Power technologies


Abstract:

N-well pockets connected to the cathode of ESD diodes may be source of parasitic electrons current in P-/P++ substrates. In this paper a methodology to reduce this latch-...Show More

Abstract:

N-well pockets connected to the cathode of ESD diodes may be source of parasitic electrons current in P-/P++ substrates. In this paper a methodology to reduce this latch-up risk is proposed. The electrical performances of this protection technique have been characterized and the results have been validated by device simulations.
Date of Conference: 10-15 September 2006
Date Added to IEEE Xplore: 22 September 2009
CD:978-1-5853-7115-0
Electronic ISSN: 2164-9340
Conference Location: Tucson, AZ, USA
STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Cornaredo, Italy

STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Agrate, Italy
STMicroelectronics, Cornaredo, Italy

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