The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation

The trade-off between T_inv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. I_on, components are analyzed in terms of N_S, v_inj and SCE in L_g= 25 nm devices for the first time. As a result, it is clarified that the aggressive T_inv scaling can achieve the performance improvement even if mu degradation occurs in some degree, because mu impact decreases with L_g and T_inv scaling impact becomes strong. Furthermore, we have introduced the effective T_inv scaling (novel SiON) process and demonstrated its excellent device performance (I_on 1 mA/mum @I_off=100 nA/mum, L_g 25 nm, V_dd=LOV, A_vt=1.8 mV mum, T_inv 1.13 nm, without any performance booster technology).

Introduction

To achieve performance requirement of 22nm node bulk planar MOSFETs, continuous scaling with HK/MG is essential because the suppression of short channel effect (SCE) is absolutely imperative [1]. However, previously reported papers show the trade-offs between scaling and the degradation in HK/MG gate stack [2]–[4]. Therefore, the impact of degradation penalty on deeply scaled devices could be a serious concern. In this study, we have investigated the degradation by device scaling optimizing gate dielectric film process conditions, and clarified the impact on short channel device performance in detail.