Introduction
To achieve performance requirement of 22nm node bulk planar MOSFETs, continuous scaling with HK/MG is essential because the suppression of short channel effect (SCE) is absolutely imperative [1]. However, previously reported papers show the trade-offs between scaling and the degradation in HK/MG gate stack [2]–[4]. Therefore, the impact of degradation penalty on deeply scaled devices could be a serious concern. In this study, we have investigated the degradation by device scaling optimizing gate dielectric film process conditions, and clarified the impact on short channel device performance in detail.