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The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation | IEEE Conference Publication | IEEE Xplore

The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation


Abstract:

The trade-off between Tinv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion, compone...Show More

Abstract:

The trade-off between Tinv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion, components are analyzed in terms of NS, vinj and SCE in Lg= 25 nm devices for the first time. As a result, it is clarified that the aggressive Tinv scaling can achieve the performance improvement even if mu degradation occurs in some degree, because mu impact decreases with Lg and Tinv scaling impact becomes strong. Furthermore, we have introduced the effective Tinv scaling (novel SiON) process and demonstrated its excellent device performance (Ion 1 mA/mum @Ioff=100 nA/mum, Lg 25 nm, Vdd=LOV, Avt=1.8 mV mum, Tinv 1.13 nm, without any performance booster technology).
Date of Conference: 15-17 June 2009
Date Added to IEEE Xplore: 11 August 2009
Print ISBN:978-1-4244-3308-7

ISSN Information:

Conference Location: Kyoto, Japan

Introduction

To achieve performance requirement of 22nm node bulk planar MOSFETs, continuous scaling with HK/MG is essential because the suppression of short channel effect (SCE) is absolutely imperative [1]. However, previously reported papers show the trade-offs between scaling and the degradation in HK/MG gate stack [2]–[4]. Therefore, the impact of degradation penalty on deeply scaled devices could be a serious concern. In this study, we have investigated the degradation by device scaling optimizing gate dielectric film process conditions, and clarified the impact on short channel device performance in detail.

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