Abstract:
Power stages are subject to severe stress due to active cycling, resulting in e.g. fast thermal cycling. While some applications require several hundred millions of cycle...Show MoreMetadata
Abstract:
Power stages are subject to severe stress due to active cycling, resulting in e.g. fast thermal cycling. While some applications require several hundred millions of cycles under normal operation conditions, ldquodisturbancesrdquo such as short circuit pose additional challenges. These issues are neither addressed by ldquoclassicalrdquo silicon wafer technology qualification nor by standard product qualification procedures. Challenges and limitations in applying the principles of Robustness Validation to these issues are discussed.
Published in: 2009 IEEE International Reliability Physics Symposium
Date of Conference: 26-30 April 2009
Date Added to IEEE Xplore: 24 July 2009
ISBN Information: