ReSim, a trace-driven, reconfigurable ILP processor simulator

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. In this paper we propose ReSim, a parameterizable ILP processor simulation acceleration engine based on reconfigurable hardware. We describe ReSim's trace-driven microarchitecture that allows us to simulate the operation of a complex ILP processor in a cycle serial fashion, aiming to simplify implementation complexity and to boost operating frequency. Being trace driven, ReSim can simulate timing in an almost ISA independent fashion, and supports all SimpleScalar ISAs, i.e. PISA, Alpha, etc. We implemented ReSim for the latest Xilinx devices. In our experiments with a 4-way superscalar processor ReSim achieves a simulation throughput of up to 28MIPS, and offers more than a factor of 5x improvement over the best reported ILP processor hardware simulators.

I. Introduction

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. Chip-multi-processors exacerbate this problem requiring the simultaneous simulation of tens or hundreds of cores, an intensive task no matter how simple the individual cores are. To accelerate the design process and increase their understanding in properties of modern processors, architects and systems designers rely on simulation tools - traditionally in software. Important characteristics of simulation models are flexibility and detail and of course performance, i.e. simulation speed. However these are conflicting goals and it is difficult to achieve all these characteristics simultaneously in one simulator.