Contents I. Introduction
Moore's law states that every two years the number of transistors on an integrated circuit doubles [1]. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates in conventional designs. This has been recognised as one of the main challenges facing the semiconductor industry which still remains unsolved. Intel were forced to make the biggest transistor re-design since the 1960s, using a metal gate with a high- gate oxide in order to reach the CMOS
Complementary Metal Oxide Semiconductor
technology node [2]. An alternative approach to modifying the materials used in the construction of MOSFETs is to optimise the circuit designs to be variability tolerant. In the past, Evolutionary Algortihms have been widely used to optimise existing CMOS designs for number of criteria, such as delay, area [3], power and yield [4]. IBM have also been investigating the use of Genetic Algortihms (GAs) to optimise their standard cell library designs [5]. The optimised designs produced are also feasible in industry, providing they are within the design tolerances of the fabrication process, as the topology itself remains unaltered.