1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture | IEEE Conference Publication | IEEE Xplore

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture


Abstract:

As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per cha...Show More

Abstract:

As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly, where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate.
Date of Conference: 08-12 February 2009
Date Added to IEEE Xplore: 29 May 2009
Print ISBN:978-1-4244-3458-9

ISSN Information:

Conference Location: San Francisco, CA, USA

Contact IEEE to Subscribe

References

References is not available for this document.