A constraint-driven methodology for placement of analog and mixed-signal integrated circuits

Layout design of analog and mixed-signal circuits is often a manual and time-consuming, trial-and-error task. Stringent constraints that must be considered simultaneously are a major reason why layout design is often not automated. To overcome this bottleneck in the design process, we present a new constraint-driven design methodology. We have verified our methodology by applying it to the placement of both analog and mixed-signal circuits. Our approach allows us to verify whether a solution that satisfies all constraints exists prior to the time consuming optimization process. If a solution exists, an initial placement with a maximum constraint robustness is constructed. Next, the initial placement is optimized. Unlike the optimization engines known so far, our implementation is driven not only by the placement objectives, but also by the adaptively weighted constraints. This allows efficient searching in the solution space of the constraints.

I. Introduction

The increasing complexity of integrated circuits (ICs) often demands integrating both analog and digital functions on a single chip. The design and synthesis of the analog parts represent a bottleneck in the design flow. This is due to the stringent analog design requirements like minimization of crossovers and isolation of sensitive nets. Moreover, analog circuits are more sensitive to the fluctuations of the manufacturing process. Thus, various constraints such as device matching, symmetry, parasitics, and thermal effects must be taken into account [1]. The combined constraints define a solution space (Fig. 1), where each candidate solution satisfies all constraints. Figure 1. Graphical representation of a solution space defined by a set of four linear constraints ck on two variables x1 and x2. The optimal solution of the respective layout problem results from minimizing (maximizing) an objective function and thus, is located on the boundary of the solution space.