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Background ADC calibration in digital domain | IEEE Conference Publication | IEEE Xplore

Background ADC calibration in digital domain


Abstract:

A 100MS/s pipelined ADC is digitally calibrated by a slow ΣΔ ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of th...Show More

Abstract:

A 100MS/s pipelined ADC is digitally calibrated by a slow ΣΔ ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR improves from 28dB to 59dB and the SFDR improves from 29dB to 68dB. The complete 0.13μ ADC SoC occupies a die size of 3.7mm×4.7mm, and consumes a total power of 448mW.
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
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Conference Location: San Jose, CA, USA

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