A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Developing digital implementations of analog and RF functions has become an area of intense investigation, motivated by low supply headroom and poor analog performance in ultra-scaled CMOS. RF frequency synthesis is particularly amenable to a digital architecture and has already seen integration benefits [1]. Nevertheless obstacles exist in the time-to-digital converter (TDC) used in an all-digital PLL (ADPLL), the equivalent of the PD and CP combination in a conventional analog PLL. To meet the requirements for wired and wireless synthesis, a synthesizer must be capable of wide-band operation as well as low spurious content, necessitating a linear TDC with fine quantization steps, such as a vernier delayline (VDL) architecture [2]; unfortunately, the architectural complexity increases sensitivity to both supply noise and device mismatch. This work introduces two techniques to ameliorate highresolution TDC performance: a precise TDC calibration algorithm and a background mismatch correction algorithm. To demonstrate the proposed techniques we have realized a 3GHz fractional synthesizer based on an 8ps resolution TDC in standard 65nm CMOS. The prototype uses a 25MHz reference and consumes 9.5mW excluding test buffers. The bandwidth is programmable from 100kHz to 2MHz, in-band phase noise is -100dBc/Hz and the worst-case in-band spur, after correction, is -45dBc. This is the first prototype with low phase noise, spur suppression and widebandwidth known to the authors. Moreover, it is competitive with fractional-N analog PLLs.