A Methodology to Evaluate the Energy Efficiency of Application Specific Processors

This paper proposes an FPGA based methodology to assess the energy efficiency of application specific processors (ASIPs). This methodology is applied to a video processing algorithm, the motion compensated frame rate conversion (MC-FRC). Previous work has shown that designing a specific instruction set can enhance the performance with a speed-up of more than 80 fold. The purpose of this work is to quantify the energy efficiency of the resulting accelerated processor. This efficiency is evaluated by estimating the power and energy consumption of the processor and of the ASIP when running the algorithm. The results obtained show that the ASIP is more energy efficient than the standard processor by a factor of at least 40. This paper describes the methodology used to compute the power and energy consumption and explains the results through a more detailed analysis of the power and energy consumption.

I. Introduction

Energy consumption is increasingly important in electronic systems; especially in battery powered embedded systems. In such systems, extending battery life while retaining computing performance (and sometimes increasing it) is often a key goal. For example, cellular phones are now able to display video, play music, or take pictures. All those multimedia features demand more and more computing power. Moreover, battery size tends to decrease as consumers desire slimmer and lighter phones. Consequently, there is strong demand for low power high-performance processors. Application specific processors (ASIPs) have already been shown to perform very efficiently in previous work [1], but their impact on energy consumption was never taken into account when such accelerations are being considered.