Abstract:
A sigma-delta capacitance-to-digital converter (CDC) with a resolution down to 19.3 aF at a bandwidth of 10 kHz, corresponding to a noise level of 0.2 aF/√Hz, is presente...Show MoreMetadata
Abstract:
A sigma-delta capacitance-to-digital converter (CDC) with a resolution down to 19.3 aF at a bandwidth of 10 kHz, corresponding to a noise level of 0.2 aF/√Hz, is presented. An integrated dielectric loss measurement circuit by means of two parallel channels with different integration times offers a complex permittivity measurement in a single-chip solution. The achieved dielectric loss angle resolution is as low as 0.3 ° for a material density ratio of 0.55 %. A test chip with two converter blocks including two 2nd order and two 4th order modulators has been produced in the austriamicrosystems AG C35B3C0 0.35 μm DPTM CMOS process, operating at a single 3.3 V supply. Applications of this circuit include mass measurement and analysis of material compositions.
Published in: 2008 Design, Automation and Test in Europe
Date of Conference: 10-14 March 2008
Date Added to IEEE Xplore: 11 April 2008
ISBN Information: