Abstract:
An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for ...Show MoreMetadata
Abstract:
An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 43, Issue: 4, April 2008)
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Leland Chang (S'99-M'03) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences in 1999, 2001, and 2003, respectively, from the University of California, Berkeley.
He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, in 2003 as a Research Staff Member and is now manager of Design and Technology Solutions. His research has spanned topics ranging from silicon CMO...Show More
Leland Chang (S'99-M'03) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences in 1999, 2001, and 2003, respectively, from the University of California, Berkeley.
He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, in 2003 as a Research Staff Member and is now manager of Design and Technology Solutions. His research has spanned topics ranging from silicon CMO...View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Robert K. Montoye (S'81–M'89) holds a B.S. degree in physics and M.S. and Ph.D. degrees in computer science, all from the University of Illinois.
Joining IBM in 1983, he designed and implemented the RS/6000 floating-point unit. After pursuing interests outside IBM from 1990 to 1995, he returned to IBM to focus on finding a lower supply circuit family with state-of-the-art performance and its impact on overall microarchitec...Show More
Robert K. Montoye (S'81–M'89) holds a B.S. degree in physics and M.S. and Ph.D. degrees in computer science, all from the University of Illinois.
Joining IBM in 1983, he designed and implemented the RS/6000 floating-point unit. After pursuing interests outside IBM from 1990 to 1995, he returned to IBM to focus on finding a lower supply circuit family with state-of-the-art performance and its impact on overall microarchitec...View more
IBM Global Engineering Services, Kyoto, Japan
Yutaka Nakamura received the B.S. degree in mechanical control engineering from Waseda University, Tokyo, Japan.
He joined IBM Japan Ltd., at the Yasu plant, Shiga, Japan and worked on semiconductor device characterization and function testing. Then he moved to the Yasu Technology Application Laboratory and has worked on various kinds of memory circuit design, characterization, function testing and CAD setup for DRAMs in 4...Show More
Yutaka Nakamura received the B.S. degree in mechanical control engineering from Waseda University, Tokyo, Japan.
He joined IBM Japan Ltd., at the Yasu plant, Shiga, Japan and worked on semiconductor device characterization and function testing. Then he moved to the Yasu Technology Application Laboratory and has worked on various kinds of memory circuit design, characterization, function testing and CAD setup for DRAMs in 4...View more
IBM Systems and Technology Group, Essex Junction, VT, USA
Kevin A. Batson received the B.S. and M.S. degrees in electrical engineering in 1989, 1993, respectively, from Polytechnic University in New York City.
He joined IBM Microelectronics in 1993 as a SRAM Circuit Design Engineer. During his 14 years at IBM, he has designed ASIC SRAM arrays technology development test sites, Power PC microprocessor two port data caches, an 18 Mb CAM Chip and various stand-alone SRAM Chips. He h...Show More
Kevin A. Batson received the B.S. and M.S. degrees in electrical engineering in 1989, 1993, respectively, from Polytechnic University in New York City.
He joined IBM Microelectronics in 1993 as a SRAM Circuit Design Engineer. During his 14 years at IBM, he has designed ASIC SRAM arrays technology development test sites, Power PC microprocessor two port data caches, an 18 Mb CAM Chip and various stand-alone SRAM Chips. He h...View more
IBM Systems and Technology Group, Rochester, MN, USA
Richard J. Eickemeyer (M'87–SM'01) received the B.S. degree in electrical engineering from Purdue University, West Lafayette, IN, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.
He is currently a Senior Technical Staff Member at IBM Corporation in Rochester, MN where he is the processor core performance team leader for IBM PowerPC servers and is working on a future processor design. Prev...Show More
Richard J. Eickemeyer (M'87–SM'01) received the B.S. degree in electrical engineering from Purdue University, West Lafayette, IN, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.
He is currently a Senior Technical Staff Member at IBM Corporation in Rochester, MN where he is the processor core performance team leader for IBM PowerPC servers and is working on a future processor design. Prev...View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Robert H. Dennard (F'79) was born in Terrell, TX, in 1932. He received the B.S. and M.S. degrees in electrical engineering from Southern Methodist University, Dallas, TX, in 1954 and 1956 respectively, and the Ph.D. degree from Carnegie Institute of Technology, Pittsburgh, PA, in 1958.
He then joined IBM Research Division where his early experience included the study of new digital devices and circuits for logic and memory...Show More
Robert H. Dennard (F'79) was born in Terrell, TX, in 1932. He received the B.S. and M.S. degrees in electrical engineering from Southern Methodist University, Dallas, TX, in 1954 and 1956 respectively, and the Ph.D. degree from Carnegie Institute of Technology, Pittsburgh, PA, in 1958.
He then joined IBM Research Division where his early experience included the study of new digital devices and circuits for logic and memory...View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Wilfried Haensch received the Ph.D. in 1981 from the Technical University of Berlin, Germany in the field of theoretical solid state physics.
After a post doc position at Indiana University, where he worked on many particle modifications of the Boltzmann transport equation with Gerald Mahan, he joint the University of Hamburg in 1983 to continue his work on many body effects in electron transport. In 1984 he joint SIEMENS ...Show More
Wilfried Haensch received the Ph.D. in 1981 from the Technical University of Berlin, Germany in the field of theoretical solid state physics.
After a post doc position at Indiana University, where he worked on many particle modifications of the Boltzmann transport equation with Gerald Mahan, he joint the University of Hamburg in 1983 to continue his work on many body effects in electron transport. In 1984 he joint SIEMENS ...View more
IBM Austin Research Laboratory, Austin, TX, USA
Damir Jamsek received the M.S. and Ph.D. degrees in electrical and computer engineering from Syracuse University in 1987 and 1990, respectively.
He joined the IBM Austin Research Laboratory in 1997 as a Research Staff Member and has managed a department engaged in VLSI research on high-speed arithmetic circuits and SRAM memory structures. His research has included design and verification of hardware, tools for analysis and...Show More
Damir Jamsek received the M.S. and Ph.D. degrees in electrical and computer engineering from Syracuse University in 1987 and 1990, respectively.
He joined the IBM Austin Research Laboratory in 1997 as a Research Staff Member and has managed a department engaged in VLSI research on high-speed arithmetic circuits and SRAM memory structures. His research has included design and verification of hardware, tools for analysis and...View more
Contents IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Leland Chang (S'99-M'03) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences in 1999, 2001, and 2003, respectively, from the University of California, Berkeley.
He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, in 2003 as a Research Staff Member and is now manager of Design and Technology Solutions. His research has spanned topics ranging from silicon CMOS technology and SRAM array design to nonvolatile memory and RF MEMS. His early efforts focused on ultra-thin body and double-gate MOSFETs for CMOS scaling and has more recently worked on scaling issues for embedded memory. He holds 6 patents and has authored more than 40 technical articles.
Leland Chang (S'99-M'03) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences in 1999, 2001, and 2003, respectively, from the University of California, Berkeley.
He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, in 2003 as a Research Staff Member and is now manager of Design and Technology Solutions. His research has spanned topics ranging from silicon CMOS technology and SRAM array design to nonvolatile memory and RF MEMS. His early efforts focused on ultra-thin body and double-gate MOSFETs for CMOS scaling and has more recently worked on scaling issues for embedded memory. He holds 6 patents and has authored more than 40 technical articles.View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Robert K. Montoye (S'81–M'89) holds a B.S. degree in physics and M.S. and Ph.D. degrees in computer science, all from the University of Illinois.
Joining IBM in 1983, he designed and implemented the RS/6000 floating-point unit. After pursuing interests outside IBM from 1990 to 1995, he returned to IBM to focus on finding a lower supply circuit family with state-of-the-art performance and its impact on overall microarchitecture and architecture. He is a member of the IBM Academy of Technology. He has published 25 technical papers and holds more than 50 patents.
Robert K. Montoye (S'81–M'89) holds a B.S. degree in physics and M.S. and Ph.D. degrees in computer science, all from the University of Illinois.
Joining IBM in 1983, he designed and implemented the RS/6000 floating-point unit. After pursuing interests outside IBM from 1990 to 1995, he returned to IBM to focus on finding a lower supply circuit family with state-of-the-art performance and its impact on overall microarchitecture and architecture. He is a member of the IBM Academy of Technology. He has published 25 technical papers and holds more than 50 patents.View more
IBM Global Engineering Services, Kyoto, Japan
Yutaka Nakamura received the B.S. degree in mechanical control engineering from Waseda University, Tokyo, Japan.
He joined IBM Japan Ltd., at the Yasu plant, Shiga, Japan and worked on semiconductor device characterization and function testing. Then he moved to the Yasu Technology Application Laboratory and has worked on various kinds of memory circuit design, characterization, function testing and CAD setup for DRAMs in 4Mb to 64Mb generations, 4T/6T/8T SRAM, Pseudo-SRAM, NOR Flash, Register File and also 4GHz Enhanced-DP CELL BE microprocessor circuit design. He is currently with IBM Japan's Global Engineering Solutions and responsible for Spin-Torque MRAM research and development.
Yutaka Nakamura received the B.S. degree in mechanical control engineering from Waseda University, Tokyo, Japan.
He joined IBM Japan Ltd., at the Yasu plant, Shiga, Japan and worked on semiconductor device characterization and function testing. Then he moved to the Yasu Technology Application Laboratory and has worked on various kinds of memory circuit design, characterization, function testing and CAD setup for DRAMs in 4Mb to 64Mb generations, 4T/6T/8T SRAM, Pseudo-SRAM, NOR Flash, Register File and also 4GHz Enhanced-DP CELL BE microprocessor circuit design. He is currently with IBM Japan's Global Engineering Solutions and responsible for Spin-Torque MRAM research and development.View more
IBM Systems and Technology Group, Essex Junction, VT, USA
Kevin A. Batson received the B.S. and M.S. degrees in electrical engineering in 1989, 1993, respectively, from Polytechnic University in New York City.
He joined IBM Microelectronics in 1993 as a SRAM Circuit Design Engineer. During his 14 years at IBM, he has designed ASIC SRAM arrays technology development test sites, Power PC microprocessor two port data caches, an 18 Mb CAM Chip and various stand-alone SRAM Chips. He holds 12 patents.
Kevin A. Batson received the B.S. and M.S. degrees in electrical engineering in 1989, 1993, respectively, from Polytechnic University in New York City.
He joined IBM Microelectronics in 1993 as a SRAM Circuit Design Engineer. During his 14 years at IBM, he has designed ASIC SRAM arrays technology development test sites, Power PC microprocessor two port data caches, an 18 Mb CAM Chip and various stand-alone SRAM Chips. He holds 12 patents.View more
IBM Systems and Technology Group, Rochester, MN, USA
Richard J. Eickemeyer (M'87–SM'01) received the B.S. degree in electrical engineering from Purdue University, West Lafayette, IN, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.
He is currently a Senior Technical Staff Member at IBM Corporation in Rochester, MN where he is the processor core performance team leader for IBM PowerPC servers and is working on a future processor design. Previously, he has worked on several different processor designs. His research interests are computer architecture and performance analysis. He has authored several papers and has been awarded 28 U.S. patents with others pending. He has been named an IBM Master Inventor.
Dr. Eickemeyer has received several IBM awards including two IBM Corporate Awards.
Richard J. Eickemeyer (M'87–SM'01) received the B.S. degree in electrical engineering from Purdue University, West Lafayette, IN, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.
He is currently a Senior Technical Staff Member at IBM Corporation in Rochester, MN where he is the processor core performance team leader for IBM PowerPC servers and is working on a future processor design. Previously, he has worked on several different processor designs. His research interests are computer architecture and performance analysis. He has authored several papers and has been awarded 28 U.S. patents with others pending. He has been named an IBM Master Inventor.
Dr. Eickemeyer has received several IBM awards including two IBM Corporate Awards.View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Robert H. Dennard (F'79) was born in Terrell, TX, in 1932. He received the B.S. and M.S. degrees in electrical engineering from Southern Methodist University, Dallas, TX, in 1954 and 1956 respectively, and the Ph.D. degree from Carnegie Institute of Technology, Pittsburgh, PA, in 1958.
He then joined IBM Research Division where his early experience included the study of new digital devices and circuits for logic and memory applications, and the development of advanced data communication techniques. Since 1963, he has been at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, where he has been involved in microelectronics research and development from the early days onward. His primary work has been in MOS transistors and integrated digital circuits using them. In 1967, he invented the dynamic RAM memory cell used in most all computers today. With coworkers he developed the concept of MOS transistor scaling in 1972, which is often cited as a guiding principle for microelectronics. He was appointed an IBM Fellow in 1979. He has contributed numerous papers on advances in CMOS technology and on prospects and challenges of scaling that technology to very small dimensions.
Dr. Dennard is a Fellow of IEEE. He received the IEEE Cledo Brunetti Award in 1982 and the Edison Medal in 2001. He is a member of the National Academy of Engineering and the American Philosophical Society, and he has received many honors including the National Medal of Technology in 1988 and induction into the National Inventors Hall of Fame in 1997.
Robert H. Dennard (F'79) was born in Terrell, TX, in 1932. He received the B.S. and M.S. degrees in electrical engineering from Southern Methodist University, Dallas, TX, in 1954 and 1956 respectively, and the Ph.D. degree from Carnegie Institute of Technology, Pittsburgh, PA, in 1958.
He then joined IBM Research Division where his early experience included the study of new digital devices and circuits for logic and memory applications, and the development of advanced data communication techniques. Since 1963, he has been at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, where he has been involved in microelectronics research and development from the early days onward. His primary work has been in MOS transistors and integrated digital circuits using them. In 1967, he invented the dynamic RAM memory cell used in most all computers today. With coworkers he developed the concept of MOS transistor scaling in 1972, which is often cited as a guiding principle for microelectronics. He was appointed an IBM Fellow in 1979. He has contributed numerous papers on advances in CMOS technology and on prospects and challenges of scaling that technology to very small dimensions.
Dr. Dennard is a Fellow of IEEE. He received the IEEE Cledo Brunetti Award in 1982 and the Edison Medal in 2001. He is a member of the National Academy of Engineering and the American Philosophical Society, and he has received many honors including the National Medal of Technology in 1988 and induction into the National Inventors Hall of Fame in 1997.View more
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Wilfried Haensch received the Ph.D. in 1981 from the Technical University of Berlin, Germany in the field of theoretical solid state physics.
After a post doc position at Indiana University, where he worked on many particle modifications of the Boltzmann transport equation with Gerald Mahan, he joint the University of Hamburg in 1983 to continue his work on many body effects in electron transport. In 1984 he joint SIEMENS corporate research in Munich to investigate high field transport in MOSFET devices. He developed a simplified hydrodynamic transport model that was implemented into the device simulator MINIMOS. He developed a complete 2D hot e-module that allowed the self-consistent evaluation of hot e effects on MOSFET degradation including the transport of carriers in the gate oxide and. In 1988 he joined the DRAM development team at the SIEMENS research lab to investigate new cell concepts. In 1990 he joined the DRAM alliance between IBM and SIEMENS to develop quarter micron 64M DRAM. In this function he was involved with device characterization of shallow trench bounded devices and cell design questions. In 1996 he moved to a manufacturing facility to build various generations of DRAM. His main function was to transfer technologies form development into manufacturing and to guarantee a successful yield ramp of the product. In 2001 he joint IBM T. J. Watson Research Center to lead a group for novel devices and applications. He is currently responsible for the 22 nm device design and other explorative technology options.
Wilfried Haensch received the Ph.D. in 1981 from the Technical University of Berlin, Germany in the field of theoretical solid state physics.
After a post doc position at Indiana University, where he worked on many particle modifications of the Boltzmann transport equation with Gerald Mahan, he joint the University of Hamburg in 1983 to continue his work on many body effects in electron transport. In 1984 he joint SIEMENS corporate research in Munich to investigate high field transport in MOSFET devices. He developed a simplified hydrodynamic transport model that was implemented into the device simulator MINIMOS. He developed a complete 2D hot e-module that allowed the self-consistent evaluation of hot e effects on MOSFET degradation including the transport of carriers in the gate oxide and. In 1988 he joined the DRAM development team at the SIEMENS research lab to investigate new cell concepts. In 1990 he joined the DRAM alliance between IBM and SIEMENS to develop quarter micron 64M DRAM. In this function he was involved with device characterization of shallow trench bounded devices and cell design questions. In 1996 he moved to a manufacturing facility to build various generations of DRAM. His main function was to transfer technologies form development into manufacturing and to guarantee a successful yield ramp of the product. In 2001 he joint IBM T. J. Watson Research Center to lead a group for novel devices and applications. He is currently responsible for the 22 nm device design and other explorative technology options.View more
IBM Austin Research Laboratory, Austin, TX, USA
Damir Jamsek received the M.S. and Ph.D. degrees in electrical and computer engineering from Syracuse University in 1987 and 1990, respectively.
He joined the IBM Austin Research Laboratory in 1997 as a Research Staff Member and has managed a department engaged in VLSI research on high-speed arithmetic circuits and SRAM memory structures. His research has included design and verification of hardware, tools for analysis and simulation of VLSI circuits and most recently the use of massively parallel multithreaded compute resources to model and predict device and circuit behavior for 45nm and beyond technology nodes.
Damir Jamsek received the M.S. and Ph.D. degrees in electrical and computer engineering from Syracuse University in 1987 and 1990, respectively.
He joined the IBM Austin Research Laboratory in 1997 as a Research Staff Member and has managed a department engaged in VLSI research on high-speed arithmetic circuits and SRAM memory structures. His research has included design and verification of hardware, tools for analysis and simulation of VLSI circuits and most recently the use of massively parallel multithreaded compute resources to model and predict device and circuit behavior for 45nm and beyond technology nodes.View more
