Abstract:
This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its impl...Show MoreMetadata
Abstract:
This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals.
Published in: 2007 IEEE International Test Conference
Date of Conference: 21-26 October 2007
Date Added to IEEE Xplore: 22 January 2008
ISBN Information:
ISSN Information:
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Function Tests ,
- Control Signal ,
- Complex Design ,
- Test Sequences ,
- Final Test ,
- Hybrid Structure ,
- Pattern Generator ,
- Test Pattern ,
- Defect Model ,
- Testing Coverage ,
- Critical Path ,
- Clock Cycles ,
- Physical Design ,
- Clock Signal ,
- Internal Modes ,
- Memory Array ,
- OR Gate ,
- Clock Control ,
- Reference Clock ,
- L2 Cache ,
- Scan Pattern ,
- Hold Time ,
- Setup Time ,
- Normal Scan ,
- Power Consumption ,
- Broken Line ,
- Control Logic
Contents Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Function Tests ,
- Control Signal ,
- Complex Design ,
- Test Sequences ,
- Final Test ,
- Hybrid Structure ,
- Pattern Generator ,
- Test Pattern ,
- Defect Model ,
- Testing Coverage ,
- Critical Path ,
- Clock Cycles ,
- Physical Design ,
- Clock Signal ,
- Internal Modes ,
- Memory Array ,
- OR Gate ,
- Clock Control ,
- Reference Clock ,
- L2 Cache ,
- Scan Pattern ,
- Hold Time ,
- Setup Time ,
- Normal Scan ,
- Power Consumption ,
- Broken Line ,
- Control Logic
