Investigation of the hysteresis phenomenon of a silicon-based piezoresistive pressure sensor

At present, the silicon piezoresistive pressure sensor is a mature technology in the industry, and its measurement accuracy is more rigorous in many advanced applications. Micro piezoresistive pressure sensor is fabricated by a MEMS process, and its main operational principle is that the external pressure loading causes the deflection, strain, and stress which occur on the silicon membrane. The environmental temperature, the humidity, and the pressure will reduce its performance. Moreover, the drifts of output voltage in the same temperature caused by the residual stress on the aluminum trace under thermal cycle loading also influence the performance of the piezoresistive pressure sensor. This is called the thermal hysteresis phenomenon, and the variation of output voltage is called the thermal hysteresis voltage. Among the critical issues of silicon piezoresistive pressure sensor, the hysteresis phenomenon should be deeply paid attention to obtain better sensor accuracy. For this reason, this research would like to investigate the effect of the external loading on the output voltage of a pressure sensor. Based on the process of pressure sensors, this research adopts the concept of pseudo temperature combined with a finite element method (FEM) to obtain the thermal hysteresis voltage. After several numerical analysis of thermal hysteresis voltage, the experiment is then performed to validate the simulation results. After being validated with the experimental results, the variation of thermal hysteresis voltage under a different trace layout is analyzed. Based on simulation results of a different trace layout, it is found that the trace line layout plays an important role in the thermal hysteresis performance of a pressure sensor, which indicates that the longer aluminum trace increases the hysteresis voltage. The uniform and symmetrical layout of aluminum trace can reduce the variation of resistance change and decrease the hysteresis voltage. Furthermore, the trace layout which is far away from the silicon membrane and piezoresistance is suggested to reduce the hysteresis voltage.