PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator

In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 processor core at a configurable level of detail ranging from RTL-level models of all key pipeline structures, caches and devices up to full-speed native execution on the host CPU. Unlike other microarchitectural simulators, PTLsim targets the real commercially available x86 ISA, rather than a discontinued architecture with limited tools and an uncertain future. PTLsim supports several flavors: a single threaded userspace version and a full system version providing an SMT model and the infrastructure for multi-core support. We first describe what it takes to perform cycle accurate modeling of a complete x86 machine at the muop (micro-operation) level, along with the challenges and requirements for effective full system multi-processor capable simulation. We then describe the internal architecture of full system PTLsim and how it interacts with the Xen hypervisor and PTLsim's native mode co-simulation technology. We experimentally evaluate PTLsim's real world accuracy by configuring it like an AMD Athlon 64 machine before running a demanding full system client-server networked benchmark inside PTLsim. We compare the statistics generated by our model with the actual numbers from the real processor to demonstrate PTLsim is accurate to within 5% across all major parameters. We provide a discussion of prior simulation tools, along with their strengths and weaknesses. We describe why PTLsim's x86 focus is highly relevant, and we use our full system simulation results to demonstrate the pitfalls of userspace only simulation. Finally, we conclude by detailing future work

1. Introduction

Microprocessor simulators have been around since the dawn of computing to serve many roles, including hardware development and debugging, providing binary compatibility and enabling performance studies. Microarchitects and researchers are generally interested in cycle accurate simulation tools, which construct a complete microprocessor pipeline in software and simulate the flow of each instruction through this pipeline, so as to collect much more accurate timing information down to individual cycles. Full system simulators take accuracy a step further by simulating all instructions in both user applications and the kernel, and may also support cycle accurate modeling of multiprocessor configurations and hardware devices inside a virtual machine.