A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm

The paper presents a GaAs 32-bit IEEE floating point multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. This chip uses a new layout methodology for easy design structure and improved GaAs technology layout density. The combination of the fast arithmetic architecture and compact layout style achieves 4ns multiplication time with 3.5 W power dissipation at 75/spl deg/C. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8/spl mu/m GaAs technology.<>