Successful Development and Implementation of Statistical Outlier Techniques on 90nm and 65nm Process Driver Devices

Burn-in and the concomitant post-burn-in retest are significant cost adders to the overall IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit analyses with parametric or non-parametric statistics, when applied to the newest technologies, result in excessive Type I or II errors which cannot be tolerated. In this paper, we describe the results from applying statistical burn-in avoidance techniques using time-zero sort test responses to driver designs fabricated in 90nm and 65nm low leakage technologies and libraries