TMC-a CMOS time to digital converter VLSI

A novel time-to-digital converter CMOS VLSI chip has been developed. The main components of this TMC are memories and delay lines (buffers in series). Low-power and high-density characteristics have been attained by a submicron CMOS process and a novel circuit scheme utilizing variable-delay elements with a feedback circuit. Test results of a prototype are described, with attention given to delay time, linearity, and stability.<>