Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS | IEEE Journals & Magazine | IEEE Xplore

Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS


Abstract:

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless p...Show More

Abstract:

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 30, Issue: 2, February 1995)
Page(s): 101 - 109
Date of Publication: 28 February 1995

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