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A test pattern for three-dimensional latch-up analysis | IEEE Conference Publication | IEEE Xplore

A test pattern for three-dimensional latch-up analysis


Abstract:

By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influ...Show More

Abstract:

By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influence the latch-up behavior of a typical CMOS structure. A 3D latch-up test pattern is designed to allow the experimental study of such effects. The first measurement results show complex behaviors that can be overlooked if common 2D test patterns are used.<>
Date of Conference: 22-25 March 1993
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-0857-3
Conference Location: Sitges, Spain

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