Parallel decomposition of multipliers modulo (2/sup n/+or-1)

The authors discuss the mathematical basis and hardware implementations of large-word length multipliers (mod 2/sup n/+or-1). The focus is on a recently developed parallel arithmetic system named the polynomial residue-number system (see A. Skavantzos, 1987). The proposed multipliers allow a variety of implementation options and are shown to have much better performance than multipliers based on traditional techniques. The performance improvement is most obvious in multiplication-intensive environments.<>