Efficient VLSI Architecture of Lifting-Based Wavelet Packet Transform for Audio and Speech Applications

This paper presents a novel VLSI architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing. Folded architecture for lifting-based wavelet filters is proposed to compute wavelet butterflies in different groups simultaneously, at each decomposition level. Internal pipelining and by-pass mode are employed on each processing element to increase computation throughput and provide easy configuration for arbitrary decomposition, respectively. According to the comparison results, our proposed VLSI architecture is more efficient than previous proposed architectures in terms of arithmetic operations, storage requirement, and throughput

1. Introduction

In the last decades, discrete wavelet transform (DWT) [1] has been successfully used in a wide range of applications, including numerical analysis, signal analysis, image and video coding, pattern recognition, statistics, and physics. As a generalization of DWT, discrete wavelet packet transform (DWPT) provides good temporal and spectral resolutions in arbitrary regions of the time and frequency (TF) plane [1]–[2]. Due to the characteristic of flexible TF decomposition, DWPT has also been widely used in many applications, especially in speech and audio coding, speech enhancement, speech recognition, hearing aid, etc.