Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems

Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by high speed, large scale implementation of SerDes I/Os (serial/deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper, we present the test challenges and describe on-chip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets