Restrictive compression techniques to increase level 1 cache capacity

Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access latency. The basic technique - all words narrow (AWN) - compresses a cache block only if all the words in the cache block are of narrow size. We extend the AWN technique to store a few upper half-words (AHS) in a cache block to accommodate a small number of normal-sized words in the cache block. Further, we make the AHS technique adaptive, where the additional half-words space is adaptively allocated to the various cache blocks. We also propose techniques to reduce the increase in the tag space that is inevitable with compression techniques. Overall, the techniques in this paper increase the average L1 data cache capacity (in terms of the average number of valid cache blocks per cycle) by about 50%, compared to the conventional cache, with no or minimal impact on the cache access time. In addition, the techniques have the potential of reducing the average L1 data cache miss rate by about 23%.

1 Introduction

CMOS scaling trends result in faster transistors and relatively longer wire delays, making it difficult to have low latency caches [9]. This is due to the long wires required to access the RAM structures. This trend has resulted in pipelined cache access and small-sized Level 1 caches. Another important parameter that affects cache design is the energy consumption in the cache [4], [13], [22]. To reduce the cache energy consumption, designers have decoupled the tag comparisons from the data access [15]. Figure 1 shows the decoupled and pipelined cache read access [11]. A cache access starts with decoding the set index. In the next cycle, byte-offset is decoded in parallel to address tag comparisons, and the bit-lines in the data array are pre-charged. The tag comparisons control whether or not the data is read from a cache block. If the data is read, then it is then driven to the units that requested the data. Figure 1: Pipelined Data Cache Read Access