FPGA technology mapping: a study of optimality

This paper attempts to quantify the optimality of FPGA technology mapping algorithms. The authors developed an algorithm, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed to realize its functionality. This technique was applied iteratively to small portions of circuits that have already been technology mapped by the best available mapping algorithms for FPGAs. In many cases, the optimal mapping of the subcircuit uses fewer LUTs than is obtained by the technology mapping algorithm. It is shown that for some circuits the total area improvement could be up to 67%.

1. Introduction

FPGAs (Field Programmable Gate Arrays) are reconfigurable integrated circuits that are characterized by a sea of programmable logic blocks surrounded by a programmable routing structure. Most modern FPGA devices contain programmable logic blocks that are based on the -input lookup table (-LUT) where a LUT contains truth table configuration bits so it can implement any -input function. Figure 1 illustrates the general structure of a 2-LUT. The number of LUTs needed to implement a given circuit determines the size and cost of the FPGA-based realization. Thus one of the most important phases of the F'PGA CAD flow is the technology mapping step that maps an optimized circuit description into a LUT network present in the target FPGA architecture. The goal of the technology mapping step is to reduce area, delay, or a combination thereof in the network of programmable logic blocks that is produced. In this work, we assess state-of-the-art FPGA technology mapping algorithms in terms of area-optimality. Timing-driven technology mapping is not covered in this study. Figure 1:

2-input LUT

Figure 2:

Technology mapping as a covering problem. (a) original netlist (b) possible covering (c) lut mapping from covering