A voltage acceleration lifetime model to predict post-cycling LTDR characteristics of split-gate flash memories

In developing a fast test methodology to predict post-cycling low temperature data retention (LTDR) lifetime of split-gate flash memories, word-line stress is used to accelerate the charge gain effect in the trap-assist-tunneling (TAT) regime. By modeling the data retention behaviors under word-line stress conditions, lifetime tests can be completed successfully in a much shorter period, providing accurate lifetime prediction more efficiently for thicker gate oxide products.