DBNS addition using cellular neural networks

This paper introduces a new architecture for implementing addition and non-zero digit reduction for the highly redundant double-base number system (DBNS). The circuitry is realized using an analog cellular neural network (CNN) approach, which naturally maps the 2D DBNS representation to a 2D analog CNN architecture. In this paper we introduce a novel architecture for a DBNS adder that uses no digital logic. The adder exploits some of the properties of the DBNS to provide limited-carry addition, and we also address the problems associated with non-zero digit reduction. The implementation using only analog circuits has the advantage of ultra-low noise for sensitive mixed-signal circuits. We present circuit simulation results of the designed circuit, using a 0.35 /spl mu/m CMOS technology, to validate the feasibility of our technique.