Latch-up failure path between power pins in the mixed-voltage process

A new latch-up failure phenomenon induced by the parasitic P-N-P-N path between power pins is reported here. This latch-up failure is observed in 0.13/spl mu/m and 0.18/spl mu/m process, but the test passes in 0.25/spl mu/m. a traditional latch-up prevention methodology of guide-ring insertion works well here, and the chip is tape-out.